Creating multi-standard, multi-resolution video engines using configurable processors
By Sumit Gupta, Product Marketing Manager, Tensilica Inc.
September 15, 2006 -- videsignline.com
Customize the processor to your video application by creating instructions, register files, functional units and interfaces that accelerate the processing.
The explosive growth of consumer electronics and, specifically, handheld devices such as cellular phones, PDAs, and portable media players (PMPs) has drastically changed the requirements placed on the end-silicon providers. These silicon providers can no longer design ICs that are targeted at only one or two multimedia codecs or wireless standards. Consumers expect their devices to play media from different sources, coded using different standards, and downloaded using a variety of different wireless standards. Therefore, a new, more flexible design approach must be taken that provides for easy adoption of new media standards. In this article, we focus on the challenges and opportunities for video decoder and encoder engines.
September 15, 2006 -- videsignline.com
Customize the processor to your video application by creating instructions, register files, functional units and interfaces that accelerate the processing.
The explosive growth of consumer electronics and, specifically, handheld devices such as cellular phones, PDAs, and portable media players (PMPs) has drastically changed the requirements placed on the end-silicon providers. These silicon providers can no longer design ICs that are targeted at only one or two multimedia codecs or wireless standards. Consumers expect their devices to play media from different sources, coded using different standards, and downloaded using a variety of different wireless standards. Therefore, a new, more flexible design approach must be taken that provides for easy adoption of new media standards. In this article, we focus on the challenges and opportunities for video decoder and encoder engines.
To read the full article, click here
Related Semiconductor IP
- Zigbee Transceiver PHY
- Data Flow Architecture IP
- AMBA SPI Controller MRAM Controller
- Ethernet MAC
- Protocol Bridges
Related Articles
- Configurable Processors for Video Processing SOCs
- Power Optimization using Multi BIT flops and MIMCAPs in 16nm technology and below
- Creating Domain Specific Processors Using Custom RISC-V ISA Instructions
- Multi-core MPEG-4 video encode partitioning
Latest Articles
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection
- BitFair: A 12nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision
- A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference
- Reducing Instruction-Fetch Energy in RISC-V for Embedded AI Processing via Dynamic and Static Loop Caching
- SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow