Multi-core MPEG-4 video encode partitioning
Partitioning a video-encoding algorithm onto a multi-core architecture can utilize a variety of techniques, including data partitioning and pipelining. Cradle Technologies explains them, and how to do MPEG-4 Baseline Profile implementation on their multi-core CT3600 processor family.
By Laurent Bonetto, Ram Natarajan, and Dr. R K Singh, Cradle Technologies
October 06, 2006 -- videsignline.com
Partitioning video processing algorithms onto multi-core architectures has been researched for decades, and over this time several techniques of varying efficiency have been developed to divide up the work among the processors. Let's take a closer look at some of these techniques, and see how video processing poses unique challenges to the multi-core processor.
By Laurent Bonetto, Ram Natarajan, and Dr. R K Singh, Cradle Technologies
October 06, 2006 -- videsignline.com
Partitioning video processing algorithms onto multi-core architectures has been researched for decades, and over this time several techniques of varying efficiency have been developed to divide up the work among the processors. Let's take a closer look at some of these techniques, and see how video processing poses unique challenges to the multi-core processor.
To read the full article, click here
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- Reusable debug infrastructure in multi core SoC : Embedded WiFi case study
- Picking the right MPSoC-based video architecture: Part 4
- Communication centric test and debug infrastructure for multi core SoC
- Software Infrastructure of an embedded Video Processor Core for Multimedia Solutions
Latest Articles
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety