Assessing patent value -- Hardware inventions
Rajeev Gupta & JP Long (Finnegan)
embedded.com (August 31, 2015)
Determining the value of a patent or a patent portfolio is no easy task. This is especially true for the semiconductor industry, where a single infringing product may be covered by hundreds—if not thousands—of other patents. Adding to this complexity, new developments in U.S. patent damages law have the potential to alter the value of semiconductor patents significantly. Recent court decisions have increasingly emphasized the importance of the smallest salable patent-practicing unit (“SSPPU”) in assessing damages for infringement. In this article, we briefly discuss how semiconductor device manufacturers might be able to take advantage of this trend to maximize the value of their own patents and to minimize their infringement liability. In a subsequent article, we will look at factors affecting the value of software inventions.
In Ericsson, Inc. v. D-Link Sys., Inc., the United States Court of Appeals for the Federal Circuit recently underscored the following principles of patent valuation:
Where the entire value of a machine as a marketable article is properly and legally attributable to the patented feature, the damages owed to the patentee may be calculated by reference to that value. Where it is not, however, courts must insist on a more realistic starting point for the royalty calculations by juries—often, the [SSPPU] and, at times, even less
To read the full article, click here
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Articles
- SoK: From Silicon to Netlist and Beyond Two Decades of Hardware Reverse Engineering Research
- LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
- OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs
- Exploring Side-Channel Protections in Hardware Implementations of PQC ML-KEM Verification
Latest Articles
- ZTA-Q: an Open-source RISC-V Platform for Accurate Quantized CNN Inference
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM
- MEGATRON: a 28nm Analog PCM CiM/Digital System-on-Chip for Edge GenAI at 57.5 TOPS/W and 1.52 Mparam/mm²