Assessing patent value -- Hardware inventions
Rajeev Gupta & JP Long (Finnegan)
embedded.com (August 31, 2015)
Determining the value of a patent or a patent portfolio is no easy task. This is especially true for the semiconductor industry, where a single infringing product may be covered by hundreds—if not thousands—of other patents. Adding to this complexity, new developments in U.S. patent damages law have the potential to alter the value of semiconductor patents significantly. Recent court decisions have increasingly emphasized the importance of the smallest salable patent-practicing unit (“SSPPU”) in assessing damages for infringement. In this article, we briefly discuss how semiconductor device manufacturers might be able to take advantage of this trend to maximize the value of their own patents and to minimize their infringement liability. In a subsequent article, we will look at factors affecting the value of software inventions.
In Ericsson, Inc. v. D-Link Sys., Inc., the United States Court of Appeals for the Federal Circuit recently underscored the following principles of patent valuation:
Where the entire value of a machine as a marketable article is properly and legally attributable to the patented feature, the damages owed to the patentee may be calculated by reference to that value. Where it is not, however, courts must insist on a more realistic starting point for the royalty calculations by juries—often, the [SSPPU] and, at times, even less
To read the full article, click here
Related Semiconductor IP
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
Related Articles
- SPAD: Specialized Prefill and Decode Hardware for Disaggregated LLM Inference
- David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design?
- IMS: Intelligent Hardware Monitoring System for Secure SoCs
- COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events
Latest Articles
- SCENIC: Stream Computation-Enhanced SmartNIC
- Agentic AI-based Coverage Closure for Formal Verification
- Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities