Decompiling the ARM architecture code
UBM TechInsights created a decompiler that decompiles ARM machine code
Serge Sourjko and Robert Krten, UBM TechInsights
EETimes (03/08/2010 12:01 AM EST)
At UBM TechInsights, we're often tasked with proving patent infringement of a software algorithm as part of our IP Management Services. An embedded algorithm can range from a sensoring technique in an appliance, to motor control, to power management scheme, to navigation algorithm, to UI control or file system on a higher end embedded device; to name a few examples. Investigating a possible patent infringement is one of the few cases where reverse engineering software is legal in spite of any license agreement to the contrary.
An issue for projects of this nature is that most modern machine code is produced from C or C++, and the process of generating machine code by an optimizing compiler is very sophisticated. Therefore, looking at low-level (machine or assembly language) instructions is a cumbersome and error-prone way of ascertaining infringement.
Decompilation is the process of taking machine language instructions and translating them into a higher-level language representation. Decompilation is more typically used for analysis of computer viruses and malware, and, sometimes to recover lost source code or make a compatible product. One popular example of a decompiler is from Hex-Rays, who sells a very good decompiler for the i386 platform as a plug-in for its IDAPro dissassembler.
Our example for this article is based on one of the most popular assembly languages for high-volume high-value consumer electronics and many other embedded devices-the ARM architecture. We found that available decompilers for ARM produce poor quality code, so we adapted and expanded the open source "Desquirr" decompiler for our needs.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Articles
- Efficient C code for ARM devices
- Migrating ARM7 code to a Cortex-M3 MCU
- Retargeting IP -> Design system compiles silicon straight from C code
- Amba bus may move MIPS into ARM territory
Latest Articles
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration
- CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace