Applications and Use of Stage-based OCV
Ahran Dunsmoor and Dr. João Geada
EETimes (5/21/2012 9:48 AM EDT)
Stage-based OCV derate tables are a systematic correction to liberty timing models to account for on chip process variation. Stage-based OCV can be used in timing and optimization tools as a fast approximation for statistical timing giving better – more accurate results and helping to close timing at smaller process nodes. While stage-based OCV provides material improvements to timing margin over a fixed global OCV derate; worst case stage-based OCV derates can still be overly pessimistic – penalizing designs for variance outside their operating region. This paper explores the contributing factors to stage-based OCV pessimism and ways to improve the tables significantly. In addition, we demonstrate that different views of design specific derates that can be used for varying design purposes from timing to optimization.
To read the full article, click here
Related Semiconductor IP
- Verification IP for C-PHY
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
Related Articles
- Evolution of VLSI Technology and its Applications
- How to use CPLDs to manage average power consumption in portable applications
- How to use FPGAs for quadrature encoder-based motor control applications
- Paving the way for the next generation of audio codec for True Wireless Stereo (TWS) applications - PART 5 : Cutting time to market in a safe and timely manner
Latest Articles
- SCENIC: Stream Computation-Enhanced SmartNIC
- Agentic AI-based Coverage Closure for Formal Verification
- Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities