API-based verification: Effective reuse of verification environment components
Bipin Patel & Manzil Shah (eInfochips)
EDN -February 22, 2017
Verification using various methodologies has become popular as it saves VE development time. Even more time can be saved if we think of possible reuse of various VE components when defining the VE architecture. The reuse of VE components at different levels is crucial to time-saving during design verification, with applications comprising block, cluster/subsystem, chip, or SoC levels, and can also result in huge time savings during post-silicon lab validation.
This paper talks about an API- (Application Program Interface) based verification approach that can be adopted for a whole segment of ASIC applications.
Let’s focus on design blocks B1, B2, and B3 of the example SoC in Figure 1. These blocks are interconnected using unique interfaces and each one of them is to be verified independently at the block level followed by cluster and chip levels.
To read the full article, click here
Related Semiconductor IP
- UALink 200G v1.0 Verification IP
- CCSDS SCCC Demapper and Turbo Decoder
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
Related Articles
- MBIST verification: Best practices & challenges
- Multi-faceted design verification
- Challenges and Benefits of Low Power Design Verification with CPF for a standalone IP
- Simplifying SoC Verification by communicating between HVL Env and processor
Latest Articles
- RFChipAgent: Multi-Agentic AI Flow for Analog/RF Chip Design
- Anechoic: Onsager-Corrected Parallel Annealing for Sub-0.1 ms Dense Max-Cut on an FPGA
- Power, Performance, and Area of HPC-Based Malware Detectors: An FPGA and Open-PDK ASIC Study
- Terracotta: Enabling the Adoption of New DRAM Techniques via a Flexible DRAM Interface and Memory Controller
- A Framework for Accelerating Transformer Inference on RISC-V for Edge AI