Reduce SoC verification time through reuse in pre-silicon validation

Amitesh Khandelwal & Ayushi Agarwal (Freescale)
EDN (July 09, 2014)

First-pass silicon

A key focus of the IC design industry is to deliver first-pass silicon, which means finding most, if not all, of the potential defects before tape-out. This is extremely difficult due to increasing design complexity, clock speeds, multi-layered software, and shrinking technology and cycle time. Each re-spin of the silicon may cost a company millions of dollars and a lot of wasted time and effort. With more and more third party IP being used in the SoC to shorten time-to-market, the task of finding bugs before silicon becomes more difficult due to limited knowledge of the external IP by the SoC engineers.

The usual approach

SoC teams have typically relied on pre-silicon emulation to ensure first-pass silicon in such a complex and dynamic environment. The emulation platform enables closer to real time software development & accelerated simulation run time to expose more defects early in the cycle. It also provides a good framework to develop post silicon validation test suite.

However the programming framework of pre-silicon environment is typically similar to post silicon validation making it difficult to run verification patterns as is. Some of the differences include

• Verification C-APIs write to fix memory locations to enable snooping by Testbench to generate Info prints.
• Clocking macros do not work since clock sources are analog and stubbed out in emulation platform.
• Memory map header files may be different in format or content.

Due to these limitations verification team often is not able to leverage the advantages provided by the emulation platform without having to make changes in the existing test suite to address the differences highlighted above.

To read the full article, click here