Analog behavioral models reduce mixed-signal LSI verification time
By Takao Ito, Chief Specialist, Toshiba Corporation
Jun 22, 2007 (12:52 PM) -- Planet Analog
Figure 1a: CPU performance and simulation verification trend; taller (blue) bars are CPU performance, lower (yellow) bars are verification times
Figure 1b: Verification time trend
Jun 22, 2007 (12:52 PM) -- Planet Analog
Smaller process geometries are making it possible to take analog components off the board and incorporate them into the chip together with the digital portions of the designs, increasing the complexity of circuits. Even though there is a rapid increase in today's processor performance, simulation for full-chip verification is still taking a long time (Figure 1a and Figure 1b).
Figure 1a: CPU performance and simulation verification trend; taller (blue) bars are CPU performance, lower (yellow) bars are verification times
Figure 1b: Verification time trend
Current methodologies are no longer sufficient or acceptable, so new verification methods are needed.
To read the full article, click here
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related Articles
- Efficient Verification and Virtual Prototyping of Analog and Mixed-Signal IP and SOCs Using Behavioral Models
- Mixed-signal SOC verification using analog behavioral models
- Reuse of Analog Mixed Signal IP for SoC Design: Progress Report (Cadence Design Systems)
- Analog & Mixed Signal IC Debug: A high precision ADC application
Latest Articles
- Terracotta: Enabling the Adoption of New DRAM Techniques via a Flexible DRAM Interface and Memory Controller
- A Framework for Accelerating Transformer Inference on RISC-V for Edge AI
- An Interleaved Parallel Dependent Quantization Hardware Architecture for H.266/VVC
- A Formal Security Analysis of CAN XL
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience