Tharas Systems Awarded Key Patents on Hardware-Assisted Verification Technology

Patents Re-enforces Leadership in High-Performance Functional Verification and Debug Technology

SANTA CLARA, Calif. — September 16, 2004 — The United States Patent and Trademark Office has awarded Tharas Systems four patents for technology that address hardware-assisted debug and functional verification. The awards represent a total of seven patents to date for Tharas Systems, Inc., a leading provider of high-performance, hardware-assisted design verification solutions.

U.S. Patent number 6,629,297 entitled, "Tracing the change of state of a signal in a functional verification system," and U.S. Patent number 6,625,786 entitled, "Run-time controller in a functional verification system," enables Tharas to embed debug infrastructure inside the hardware-assisted engine. Using this infrastructure, designers can gain visibility over any signal during an entire duration of the test without re-construction. U.S. Patent number 6,691,287 entitled, "Functional verification system suited for verifying the function of non-cycle integrated circuits (IC) design," and U.S. Patent number 6,629,296 entitled, "Functional verification of cycle-based integrated circuit design," enables delivery of a unique, cost-effective and scalable solution for high-performance, hardware-assisted verification of complex integrated systems. It covers the fundamental chip and system technology along with its applications towards functional verification.

"Our broad patent portfolio demonstrates Tharas' dedication to technological advancement within the EDA industry," said Rahm Shastry president and CEO of Tharas Systems. "Tharas was founded on the belief that an integrated debug technology is critical with more than 70 percent of a typical design time spent in verification and at least half of that spent chasing bugs."

"Tharas technologists constantly look for innovative opportunities to benefit our customers and technology partners. We continue to focus our energy on innovations that directly benefit our customers and enhance our intellectual property," said Subbu Ganesan, chief technology officer of Tharas Systems.

About Tharas Systems

Founded in 1998, Tharas Systems is privately held with corporate headquarters located at 2518 Mission College Blvd., Suite 101, Santa Clara, CA 95054. Its high-performance verification technology leads to significant shortening of the verification cycle and material reduction in time-to-market for designers of complex integrated circuits and electronic systems. Tharas Systems Hammer custom-processor based hardware-assisted verification solution works in conjunction with popular Verilog and VHDL-based software simulators from Synopsys (NASDAQ: SNPS), Cadence Design (NYSE: CDN) and Mentor Graphics (NASDAQ: MENT). Visit Tharas Systems at http://www.tharas.com. For more specific product information or call 1-408-855-3200.

Hammer(R) is a trademark of Tharas Systems Inc. Tharas acknowledges trademarks or registered trademarks of other organizations for their respective products and services.