QualCore Logic Joins Tower Semiconductor's Authorized Design Center (TADC) Program
Sunnyvale, Calif., November 22, 2004
–– Tower Semiconductor Ltd. (Nasdaq: TSEM, TASE: TSEM) today named QualCore Logic Inc., an intellectual property (IP) and full-service, application specific integrated circuit (ASIC) realization company, a member of the Tower Authorized Design Center (TADC) program.
TADC program was created to help Tower’s customers accelerate the design-to-silicon process and enhance first-time silicon success. It links Tower Semiconductor to leading integrated circuit (IC) design firms such as QualCore Logic, providing hardware designers with qualified support for the Tower Semiconductor fabrication flow.
QualCore Logic offers a full spectrum of design services, from register transfer level (RTL) development to fully verified GDSII, including comprehensive analog and mixed-signal development capabilities. In addition to these services, customers can also take advantage of QualCore Logic’s broad portfolio of analog and digital intellectual property (IP) blocks that target Tower Semiconductor’s foundry processes.
“Tower’s criteria for this program is rigorous,” said Doron Simon, President of Tower Semiconductor USA. “QualCore Logic needed to demonstrate its ability to provide proven, high-quality services and create designs that comply with our design and verification rules, and they have done it in a clear and decisive manner. QualCore Logic complements Tower’s value added foundry services and enables us expand our analog and mixed signal design support locally to our Silicon Valley customers base.”
Adds Mahendra Jain, president of QualCore Logic: “Qualifying for the Tower Authorized Design Center program reinforces our commitment to delivering quality design services and Intellectual Properties (IP). Tower’s customers can confidently engage with QualCore Logic and be assured of first-pass silicon success.”
About Tower Semiconductor Ltd.
Tower Semiconductor LTD. is a pure-play independent wafer foundry established in 1993. The company manufactures integrated circuits with geometries ranging from 1.0 to 0.13 micron; it also provides complementary technical services and design support. In addition to digital CMOS process technology, Tower offers advanced non-volatile memory solutions, mixed-signal and CMOS image-sensor technologies. To provide world-class customer service, the company maintains two manufacturing facilities: Fab 1 has process technologies from 1.0 to 0.35 micron and can produce up to 16,000 150mm wafers per month. Fab 2 features 0.18-micron and below process technologies, including foundry-standard technology. Fab 2, when fully equipped, is will offer full production capacity of 33,000 200mm wafers per month. The Tower website is located at www.towersemi.com.
About QualCore Logic
QualCore Logic provides analog/mixed-signal ASIC design implementation and delivery of packaged and tested digital, mixed-signal and analog systems-on-chip (SoCs), based on silicon-proven IP. It can take an engineering or register transfer level (RTL) specification to GDSII through final silicon, and has designed multiple 10-million gate chips implemented in .13 micron and other process technologies. It operates design and support centers in Sunnyvale , Calif. , and Hyderabad , India . Corporate headquarters is located at: 1289 Anvilwood Avenue , Sunnyvale , Calif. 94089. Telephone: (408) 541-0730. Facsimile: (408) 541-0731. Web Site: http://www.qualcorelogic.com
###
QualCore Logic Inc. acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
Related Semiconductor IP
- Verification IP for C-PHY
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
Related News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- StarIC opens design center in The Netherlands
- TSMC to Open EU Design Center in Munich in Q3
- Rapidus announces collaboration with Siemens for 2nm semiconductor design
Latest News
- Tord Larsson-Steen appointed new CEO of Shortlink
- GUC Collaborate with Wiwynn to Advance Silicon-to-System Infrastructure for Next-Generation Hyperscale AI
- Two Weebit Nano product customers tape-out; one already demonstrating a functional prototype
- JEDEC Advances DDR5 MRDIMM Ecosystem with New Memory Interface Logic and Expanded MRDIMM Roadmap
- Altera Brings Determinism to Physical AI Systems with Latest Release of FPGA AI Suite