VIP Architecture: Why Native SystemVerilog and UVM?
January 14, 2015
Four years ago, we talked to several key customers, and decisively moved all our VIP development to an architecture based on SystemVerilog and UVM. In this short video, you can learn about the benefits of using such VIP for verifying your SoCs: ease-of-use, productivity and accelerated coverage closure.
Related Semiconductor IP
- SMC 2nm 1V8 ESD Power Clamp – Low Leakage
- TSMC 2nm 1V8 ESD Local Clamp – Low Leakage
- Zigbee Transceiver PHY
- Data Flow Architecture IP
- AMBA SPI Controller MRAM Controller
Related Blogs
- Avoiding Redundant Simulation Cycles for your UVM VIP with a Simple Save-Restore Strategy
- Key Advantages of Synopsys Memory VIP Architecture
- How to Integrate AXI VIP into a UVM Testbench
- Start using AXI VIP with some basic understanding of UVM
Latest Blogs
- Introducing SKL: The SiFive Kernel Library
- IDS-NoC: A Scalable Interconnect Solution for Modern SoC Design
- Leading-edge AI IC designs demand comprehensive HAV methodologies
- Beyond the Fab: Building Europe’s Next Generation of Semiconductor Champions
- AI Semiconductor Design at 3nm and 2nm: Silicon-Proven IP