Key Advantages of Synopsys Memory VIP Architecture
February 6, 2015
Following on his recent talk about why Synopsys chose a SystemVerilog Architecture for interface VIP, here Synopsys R&D Director Bernie DeLay talks about how a similar architecture based on SystemVerilog for Memory VIP brings some key advantages for verifying the memory interfaces in your SoC design and memory controller IP
Related Semiconductor IP
- UALink 200G v1.0 Verification IP
- CCSDS SCCC Demapper and Turbo Decoder
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
Related Blogs
- Verification of UALink (UAL) and Ultra Ethernet (UEC) Protocols for Scalable HPC/AI Networks using Synopsys VIP
- VIP Architecture: Why Native SystemVerilog and UVM?
- Memory VIP Challenges
- Performance Advantages of Synopsys VIP