How to Integrate AXI VIP into a UVM Testbench
February 27, 2015
Here, Synopsys VIP manager Tushar Mattu describes how best we can integrate AXI VIP into a UVM Testbench
Related Semiconductor IP
Related Blogs
- How to Integrate uvm_reg with AXI VIP
- Start using AXI VIP with some basic understanding of UVM
- Avoiding Redundant Simulation Cycles for your UVM VIP with a Simple Save-Restore Strategy
- VIP Architecture: Why Native SystemVerilog and UVM?
Latest Blogs
- Pioneering Secure-by-Design in the Age of the European CRA
- Overcoming power management IP challenges
- Running OpenCode with llama.cpp and Qwen 3.5 on E-Series
- Automated, Faster Specification to Sign-Off with IDS-AI
- NovaTech Automation Crius PIU: Bringing Conventional Instrument Transformers onto the IEC 61850 Process Bus