Verifying CXL 3.1 Designs with Synopsys Verification IP
As Machine Learning and Artificial Intelligence is becoming pervasive, workloads are also increasing on virtual machines and components. Industry needs mechanisms that can prioritize workloads and guarantee performance. The Compute Express Link (CXL) is an open industry-standard interconnect between processors and devices such as accelerators, memory buffers, smart network interfaces, persistent memory, and solid-state drives. CXL offers coherency and memory semantics with bandwidth that scales with PCIe bandwidth while achieving significantly lower latency than PCIe.
As a general device interconnect for graphics processing units (GPUs), general purpose graphics processing unit (GP-GPUs), field programmable gate arrays (FPGAs), CXL uses the Peripheral Component Interconnect-Express® (PCI-Express® or PCIe®) serial interface. CXL also targets memory which is traditionally connected to the CPU through the Double Data Rate (DDR) parallel interface.
A new feature of the CXL protocol allows memory pooling enhancements and requires distributed memory management. It also raises the requirement of devices to be assembled dynamically during run time while attached to a virtual machine, which leads to significantly better resource usage and lower cost due to increased multiplexing opportunities.
These requirements create a need for CXL to be further enhanced and deployed to provide high reliability with low latency load store access, and more receptive quality of service enhancements.
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