Using SystemC TLM Modeling To Solve AI Data Movement Challenges

By Andy Nightingale

May 29, 2026

In AI silicon, the performance numbers tell only part of the story. Marketing claims often highlight headline metrics such as trillions of operations per second, tensor throughput, matrix dimensions, and accelerator density. But engineers building these systems understand the harder truth. Compute performance matters only when data arrives at the right rate, with the right latency, and without starving the engines that process it.

At the beginning of an AI design project, early exploration is critical. Before teams commit to an architecture, they need to understand how the system behaves under real workload conditions. A block diagram is only a starting point. Engineers need to change assumptions, run use-case-based simulations, and quickly compare architectures. They need to find where bottlenecks start. Teams need to see which paths need more bandwidth, which flows need priority, and whether the system can keep latency-sensitive transactions moving while bulk data transfers continue.

Managing data movement has become a central focus in AI chip design. That is where SystemC transaction-level modeling (TLM) becomes useful. This gives teams a way to study packetized data as it moves through the network-on-chip (NoC), explore behavior, test performance assumptions, and understand whether the interconnect can support the workload before the design reaches RTL.

AI data movement

AI workloads are not uniform. High-volume data flows depend on sustained bandwidth, while control traffic is smaller and more latency-sensitive. Activation movement, intermediate writebacks, and new reads can overlap, creating changing demand on the NoC interconnect. Some transfers must stay coherent so processors and accelerators see the correct version of shared data. In contrast, high-bandwidth accelerator data movement may be better kept outside the coherent domain, depending on the architecture. At the same time, multiple engines may read from memory while other blocks update control structures or move completed results.

To read the full article on Semiconductor Engineering, click here.

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