Optimizing Quality-of-Service in a Network-on-Chip Architecture
The Linley Group is well-known for their esteemed Microprocessor Report publication, now in its 28th year. Accompanying their repertoire of industry reports, TLG also sponsors regular conferences, highlighting the latest developments in processor architecture and implementation.
One of the highlights of the conference was the presentation from Benoit de Lescure, Director of Application Engineering at Arteris, and Marc Greenberg, Director of Product Marketing at Synopsys. Benoit provided an update on Network-on-Chip (NoC) architecture design, with an emphasis on optimizing transactions to the unique capabilities of LPDDR4 memory. Marc joined Benoit, to describe how the Synopsys memory controller IP integrates with the new Arteris NoC memory transaction scheduling unit for LPDDR4.
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Related Semiconductor IP
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
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- FlexWay Interconnect IP
- Ncore Multi-Die Interconnect IP
- Magillem Registers
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