Model your IPs and your NoCs

By Rocco Jonack

June 17, 2026

When chip design and verification teams start a new project, they recognize the need for models that capture the design at a high level of abstraction. However, they tend to focus on acquiring or creating models of the IP blocks used to implement the device’s core functionality, while overlooking network-on-chip (NoC) interconnect IP until it’s too late.

Modeling and simulation evolution

As chip designs grew from a handful of gates in the 1970s to hundreds of IP blocks connected by complex interconnect fabrics in the 2020s, modeling and simulation evolved to keep pace. Early approaches modeled everything at the gate level, providing complete visibility, but they quickly became impractical as complexity increased.

The industry’s first major step up in abstraction was the register transfer level (RTL). These models describe how data moves between registers on each clock cycle, maintaining bit-level and cycle-level accuracy. To this day, RTL simulation remains the gold standard for functional correctness and final sign-off. The trad-eoff is speed. Because the RTL models every signal transition, meaningful simulations can take hours or even days.

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