Why your Internal IP Reuse Strategy is not Working
February 2, 2010
Internal IP reuse is something that every business wants, although the current scorecard indicates these objectives are not being met. A fairly large gap exists between leadership's vision of an ideal internal IP reuse strategy and the implementations in place today. Management views IP reuse as an essential ingredient of quicker time to market while the design communities perceive it as a road plagued with dangerous potholes. Reality - continue overlooking the designer's needs and internal reuse will remain a distant vision.
To read the full article, click here
Related Semiconductor IP
- DFI 6.0 Verification IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
Related Blogs
- Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy
- Tips on Using e Macros to Raise Abstraction and Facilitate Reuse
- ST-Ericsson (Part 3): Strategy And Outlook
- ARM furthers its "cover the earth" strategy with introduction of R5 and R7 core variants for fast, real-time, deterministic SoC applications