Closing the Gap in SoC Open Standards with RISC-V
The semiconductor industry has changed hugely in the last 3 or 4 decades. Around 1980 some larger semiconductor companies were strongly vertically integrated, not only designed and manufactured their products, but even made their own processing equipment and in-house EDA tools. Today almost every semiconductor company uses 3rd party equipment for IC manufacturing and designs using 3rd party EDA tools and 3rd party IP. A key reason why the disaggregation of the semiconductor industry has happened is the use of open standards.
There is no universally agreed definition of an open standard but it is generally agreed that they are available on a reasonable and non-discriminatory basis. In many cases, especially in SoC design, such standards are available on a royalty-free basis. Many open standards are owned by independent bodies such as the IEEE, OSI and IETF (internet engineering task force) rather than by companies. In such cases the further development of the standard is through an open process with widely-based participation.
To read the full article, click here
Related Semiconductor IP
- RISC-V Debug & Trace IP
- RISC-V IOPMP IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
- Multi-core capable RISC-V processor with vector extensions
Related Blogs
- The 5 Biggest Challenges in Modern SoC Design (And How to Solve Them)
- Implementing Dual-core Lockstep in the CHIPS Alliance VeeR EL2 RISC-V core for safety-critical applications
- Implementing I3C Host Controller support in the open source I3C Core
- Open standards: Enabling high performance infrastructure systems with CCIX
Latest Blogs
- Beyond Trusted: What the NSA’s New Guidance Means for Hardware Security
- A scalable, shader-programmable vector graphics GPU core for low-power MCUs
- Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects
- Embedded Security explained: Digital signatures
- Hardware security verification must go beyond functional testing