Cadence Go (war-game) strategy
I was attending to CDN-Live in Munich last week, so I was expecting Cadence to announce new IP related acquisition like Lip-Bu Tan did last year (Cosmic Circuit, Evatronix and Tensilica). In fact, Lip-Bu was not in Munich and Charlie Huang, SVP Worldwide Field Operations and System & Verification Group, was holding the morning keynotes for Cadence. The announcement of immediate availability of DDR4 PHY IP built on TSMC 16FinFET process is certainly an important milestone, as the Memory Controller market segment has became the largest of the Interface IP last year, passing $100 million revenues… but it’s not like claiming the acquisition of an IP vendor like Tensilica!
Listening to presentations leaves your mind some spare time, and I was thinking about Cadence IP strategy, and about Cadence global strategy. I am sure that Wall Street would love to hear that one of the Top three EDA and IP giant has decided to buy one of the remaining two, like Cadence buying Mentor Graphics for example. Wall Street would love it because it’s easy to understand (number #2 buy number #3 to become number #1) and because a lot of money and shares are moving fast (even if you get a few % of the deal, the larger the deal, the larger your commission). But if you are not working at Wall Street but within the electronic industry, trying to understand what are the dynamics of this industry, you quickly realize that such a merge is likely to lead to a disaster. There are probably a lot of redundant products, as well as redundant peoples, and these two companies have a strong company culture-but not the same!
To read the full article, click here
Related Semiconductor IP
- Highly scalable performance for classic and generative on-device and edge AI solutions
- MIPI CSI-2 TX Controller
- 1.6T Ultra Ethernet Controller
- HBM4E PHY and controller
- HBM3 PHY
Related Blogs
- Media Tablet Strategy from Google and Microsoft: illusion about the effective protection of NDAs...
- ST-Ericsson (Part 3): Strategy And Outlook
- Why your Internal IP Reuse Strategy is not Working
- ARM furthers its "cover the earth" strategy with introduction of R5 and R7 core variants for fast, real-time, deterministic SoC applications
Latest Blogs
- Building the engine behind Arm’s silicon shift
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects