Breakthrough in area efficiency of on-chip ESD protection
November 13, 2023
ESD protection in the most advanced FinFET technology is challenging: The ESD design window (link) is extremely narrow in FinFET processes (link). Moreover, some of the conventional ESD solutions like the ggNMOS based protection are not effective anymore (link).
To protect sensitive FinFET circuits IC designers need to design the traditional ESD clamps and diodes a lot bigger. It is also required to reduce the distance between rail clamps and interface pads. It leads to an increase in ESD related area and increase in parasitic capacitance at the interfaces from scaling up the ESD (dual) diodes.
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