An Steegen's Secrets of Semiconductor Scaling

By Cadence

June 27, 2016

If you were asked where in the world the most leading-edge semiconductor research is done, you'd probably pick the US or perhaps Taiwan. But the real answer is Belgium. Not even Brussels, but Leuven, a small town about 15 miles to the east where imec is located. imec holds a number of technology forums each year, the largest in Brussels for two days in May, and a shorter half-day one the day before Semicon West in San Francisco in July. One of the highlights is always listening to An Steegen, who is in charge of process technology at imec. It is like drinking from a fire hose but you get an update on what the funnel of new semiconductor technologies looks like and where the consensus seems to be coalescing around the technologies that the industry will adopt.

An said that for years designers have had "happy scaling" where PPA all improves due to Moore's Law and Dennard scaling: More transistors for the same cost and the same power density. But that has all broken down. Dennard scaling assumes that almost all the capacitance is due to the transistors, but that's not been true for a long time. For a decade, we've not had happy scaling, which leads to dark silicon, the capability to put a lot of transistors on a chip but not to fire them all up at once.

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