HBM2 gets an upgrade as semiconductor industry eyes HBM3
JEDEC recently updated its JESD235 High Bandwidth Memory (HBM) DRAM standard. As we’ve previously discussed on Rambus Press, HBM DRAM supports a wide range of use cases and verticals including graphics (GPUs), high performance computing (HPC), servers, networking and client applications. Indeed, HBM is particularly suitable for hardware that demands peak bandwidth, bandwidth per watt and capacity per area.
Densities up to 24GB, speeds hit 307 GB/s
According to JEDEC, the updated HBM standard leverages wide I/O and TSV technologies to support densities up to 24 GB per device – at speeds up to 307 GB/s. This bandwidth is delivered across a 1024-bit wide device interface that is divided into 8 independent channels on each DRAM stack. In practical terms, this means the standard can support 2-high, 4-high, 8-high, and 12-high TSV stacks of DRAM at full bandwidth, thereby enabling system flexibility for capacity requirements from 1 GB – 24 GB per stack
To read the full article, click here
Related Semiconductor IP
- HBM2E and HBM2 FPGA IP
- HBM2 Controller IIP
- HBM2 Memory Controller
- HBM2E Synthesizable Transactor
- HBM2E DFI Synthesizable Transactor
Related Blogs
- Building a robust HBM2 PHY
- HBM2 continues to ramp
- Rambus highlights HBM2 PHY collaboration at GLOBALFOUNDRIES Technology Conference
- HBM3: Next generation memory standard for solving high density and complex computational problems
Latest Blogs
- A Repeatable Framework for Hardware Security Assurance
- Inside the SiFive Performance™ P570 Gen 3: High Performance Efficiency for Next-Generation Consumer and Commercial Applications
- What the steam engine can teach us about modern chip design
- Automotive silicon in the era of AI, functional safety, and cybersecurity
- JPEG XS Officially Joins GenICam, The Machine Vision Standard Managed By EMVA