How Is the Semiconductor Industry Handling Scaling: Is Moore's Law Still Alive?
The chip design industry is going through exciting times. Process nodes with smaller geometries have always enticed chip manufacturers and OEMs, as it helps integrate more functionality over SoC. This reduction in the process nodes has been predicted by Moore's law and achieved through scaling rules as per Dennard's law.
Moore's law held for decades, but with the effective upper bound of clock frequencies, quantum tunneling and interconnects limitations, etc., it is on the deathbed. In addition, as shown in the figure, maximum clock frequency has decreased, and even single-thread performance improvements have slowed considerably.
To read the full article, click here
Related Semiconductor IP
- DSP-Based 112G SerDes
- XTAL oscillator in TSMC-7nm
- GPU
- V-by-One Verification IP
- AI model compression IP
Related Blogs
- A Trillion-Dollar Industry: How AI Is Reinventing EDA and Semiconductors
- How Physical AI Is Redefining the Automotive Industry
- Scaling for Success: How Weebit is Preparing for its Next Phase of Growth
- How is RISC-V’s open and customizable design changing embedded systems?
Latest Blogs
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- One Key for Every Door: How Aliro Extends the UWB Digital Key Beyond the Car
- Reprogrammable Post-Quantum Security for SoCs: Why Crypto-Agility Matters
- Designing the Beam Steering Core for a C-Band AESA: A Look at VSI's VBF0644 GaAs Beamformer IC
- Secure Boot for embedded systems: Building a complete chain of trust