System Scaling Key to Semiconductor Progress

By EETimes

June 27, 2016

System scaling technologies exist but can't go mainstream until IC designers and manufacturing experts cooperate.

Advanced semiconductor nodes below 10nm promise tens of billions of gates and memory bits, yet the current strategy of transistor scaling has reached its practical limits for most applications. Only the largest companies are likely to invest in SoCs at 7nm or 5nm where high-volume applications like today’s smartphones offer the potential payback to justify the risks and high development costs in the range of hundreds of millions of dollars.

System scaling may be the answer. While it is not a new concept, it is taking center stage as the market looks for integration alternatives to traditional transistor scaling. It offers another path to pursuing Moore’s Law by moving the integration focus from the transistor to the system.

System scaling — often referred to as multi-die IC — encompasses the concept of integrating complex systems at the functional/building block level as opposed to the transistor level. It is based on the integration and packaging of multiple die using a variety of different advanced packaging technologies including, 3D IC, 2.5D IC, wafer level packaging (WLP), and the like. System scaling does not replace the need for the SoC which will remain as a key functional component of the system or, in die-form, a key building block of a multi-die IC.

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