16Gbps SerDes Multiprotocol Multilink PHY IP
January 18, 2016
In any advanced node, one of the most important pieces of IP is a high-performance SerDes PHY. Of course, what counts as high-performance depends on the node. At the current 16nm node, 16Gbps is the sweet spot. The reason that SerDes is so important is that almost all interface IP such as PCIe, USB, SATA, and more rely on a SerDes PHY to handle the interfaces between the SoC and the outside world. A clean PHY is one where the signals are well enough shaped that decoding them at the receiver works flawlessly. I'm sure you've seen plenty of eye diagrams showing off how clean the signal is with a large eye so that the difference between a 1 and a 0 is clearly detectable.
To read the full article, click here
Related Semiconductor IP
- 16Gbps SerDes IP on TSMC 12nm
- 16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+
- PHY for PCIe 4.0
- PCIe Express Gen4 / Ethernet SERDES on TSMC CLN5A
- PCI Express Gen4 SERDES PHY on Samsung 7LPP
Related Blogs
- New 16Gbps Multi-link, Multi-protocol SerDes PHY Enhances Datacenter Connectivity
- Rambus showcases 56G Multi-Protocol SerDes (MPS) PHY at the Samsung Foundry Forum
- 32G Multi-Protocol SerDes PHY Out the Gate
- Accelerating Your Development: Simplify SoC I/O with a Single Multi-Protocol SerDes IP
Latest Blogs
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- One Key for Every Door: How Aliro Extends the UWB Digital Key Beyond the Car
- Reprogrammable Post-Quantum Security for SoCs: Why Crypto-Agility Matters
- Designing the Beam Steering Core for a C-Band AESA: A Look at VSI's VBF0644 GaAs Beamformer IC
- Secure Boot for embedded systems: Building a complete chain of trust