MIPI Controller IP, CSI-2 Transmitter, High-Speed 80Mbps to 1.5Gbps per data lane, Soft IP
MIPI Transmitter Controller.
- MIPI
MIPI Controller IP, CSI-2 Transmitter, High-Speed 80Mbps to 1.5Gbps per data lane, Soft IP
MIPI Transmitter Controller.
MIPI Controller IP, DSI Peripheral, Soft IP
MIPI DSI Peripheral Controller.
MIPI Controller IP, DSI Host, Soft IP
DSI Host Controller.
MIPI Controller IP, CSI-2 Receiver, High-Speed 80Mbps to 1.5Gbps per data lane, Soft IP
MIPI CSI Receiver Controller.
The LLI Controller connects two chips together to create a single “virtual chip”, with both chips sharing the same memory.
MIPI RX controller on SMIC 28nm
MIPI RX controller is a mass production IP in SMIC 28nm supported MIPI DSI & DCS protocols.
The MIPI I3C Controller IP is a optimized and technology agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both …
Audio data transport The Controller IP for MIPI® SoundWire® v1.2 is a fully verified, configurable, digital core that is complian…
The MIPI DSI-2 controller core is optimized for high performance, low power and small size.
The MIPI CSI-2 controller core is optimized for high performance, low power and small size.
MIPI I3C Controller and Target Functionality
The MIPI I3C Controller IP is compliant with the I3C specification and delivers higher bandwidth and scalability for integrating …
MIPI I3C Controller Host/Target IP
MIPI I3C Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for …
MIPI I3C controller delivers high bandwidth and scalability for integration of multiple sensors
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processor…
MIPI SPMI Controller or Target
The SPMI-CTRL core implements a featured, easy-to-use controller for the MIPI System Power Management Interface (MIPI-SPMI) bus.
Controller IP for the MIPI I3C interface Compliant with the MIPI® I3C® specification and legacy compatible with the I2C specifica…
MIPI CSI Controller Subsystems
The Xilinx MIPI CSI2 Receiver Subsystem and MIPI CSI 2 Transmitter Subsystems implement the Mobile Industry Processor Interface (…
I3C Controller IP – Master / Slave, Parameterized FIFO, APB Bus. I3C Basic Specification Design
The DB-I3C-BASIC-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI …
I3C Controller IP – Master, Parameterized FIFO, APB Bus
The DB-I3C-M-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – I…
I3C Controller IP – Master / Slave, Parameterized FIFO, APB Bus
The DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – …
MIPI SoundWire Slave Controller 1.2
MIPI SoundWire®Slave Controller, typically integrated into audio DSP/Codecs or directly into audio peripherals such as Microphone…