PLL IP Listing

The 64G SerDes PHY is a configurable PHY capable of supporting speeds up to 64Gbps within a single lane.

• Multi-Protocol PHY

The WEA20SFMCWI22G is an ultra-linear FMCW modulator consisting of 3 integrated PLLs.

• GlobalFoundries
• 22nm
• FDX

The ODT-AFE-1T1R-12 is an ultra-high-performance AFE designed in a 12nm process.

• Analog Front End
• In Development
• Contact Vendor

The ODT-AFE-4T4R-12nm is an ultra-high-performance AFE designed in a 12nm CMOS process.

• Analog Front End
• In Development
• Contact Vendor

Extoll’s SerDes architecture is based on digital design elements and methodologies.

• GlobalFoundries
• 12nm
• LP

Extoll’s SerDes architecture is based on digital design elements and methodologies.

• GlobalFoundries
• 12nm
• LP

The D-PHY specification, version 1.2, is completely complied with by the MIPI D-PHY Analog TX IP Core.

• MIPI D-PHY

The DDR4 multiPHY is a mixed-signal IP solution designed to provide LPDDR3/LPDDR2/DDR3/DDR3U/DDR3L/DDR4 SDRAM connectivity in a S…

• Controller + PHY + 1
• DDR4

The MIPI D-PHY Bidirectional 2-Lane(4-Lane) macro implements the physical layer of bidirectional universal lanes for the MIPI D-P…

• MIPI D-PHY

The MIPI D-PHY Analog TX IP Core fully complies with version 1.2 of the D-PHY specification.

• MIPI D-PHY
• TSMC
• 40nm
• LP
• In Production

The MIPI D-PHY Tx IP Core is fully compliant with the D-PHY specification, version 1.2, ensuring adherence to industry standards.

• MIPI D-PHY
• TSMC
• 16nm
• FFC
• In Production

The eDisplay Port v1.4 Rx PHY IP Core caters to chips requiring high-bandwidth communication with minimal power consumption.

• Controller + PHY + 1
• SMIC
• 40nm
• LL
• In Production

The maximum capacity of the Display Port 1.4 Rx IP Channel is supported.

• Single-Protocol PHY
• In Production
• Immediate

The ODT-AFE-8A1P-T16 is an ultra highperformance AFE designed in a 16nm CMOS process.

• TSMC
• 16nm

Compliance with the PCIe 3.0 Base Specification is standardized by the PCIe 3.0 PHY IP with PIPE 4.3 interface standard.

• SMIC
• 40nm
• LP
• In Production

The MIPI D-PHY Tx IP Core fully complies with version 1.2 of the D-PHY specification.

• MIPI D-PHY
• TSMC
• 28nm
• HPC+
• In Production

The Actt's 6.25G SerDes IP is a 4-Channel Serdes configuration with 1 PLL, 4 TX channels and 4 RX channels.

• Multi-Protocol PHY
• Available on request

IGAAFEV04A is a 500 MHz analog front-end circuit.

• TSMC
• 12nm
• FFC
• Silicon Proven

IGAAFEV03A is a high speed analog front-end circuit for 5GNR application which supports 4T4R.

• TSMC
• 12nm
• FFC
• Pre-Silicon

IGPD2DY01A is a high-speed Die-to-Die interface PHY that transmits data through TSMC packaging solutions: Integrated Fan-Out (InF…

• TSMC
• 5nm
• N5FF
• Available on request