Vendor: Extoll GmbH Category: Multi-Protocol PHY

32G Multi Rate Very Short Reach SerDes PHY - GlobalFoundries 12LP and 12LPP

Extoll’s SerDes architecture is based on digital design elements and methodologies.

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GlobalFoundries 12nm LP View all specifications

Overview

Extoll’s SerDes architecture is based on digital design elements and methodologies. Plain analog blocks are only used where absolutely necessary. Various digital control and tuning loops are employed to achieve robust performance across process and operating conditions. This allows a maximum of flexibility and reduces the effort for migration to alternate target technologies. The design itself is complemented by the comprehensive advanced verification and modeling methodology employed by Extoll.

A single SerDes PHY block can consist of up to 4 bidirectional lanes and one common PLL that can be driven at various input reference clock frequencies to achieve line rates ranging from 1.25 to 32Gbps. Multiple PHY blocks can be combined to construct wider links.Moreover, the PHY IP can be adapted to custom requirements easily.

The IP enables the smallest footprint of a multi rate multi protocol and long reach SerDes Interface in the industry with lowest power consumption and channel support of up to 12 dB insertion loss for very short reach applications.

Extoll´s SerDes is best suited to support high-speed data applications in Industrial, Aerospace, Automotive, HPC and QC segments.

Key features

  • Line rates from 1.25 up to 32Gbps
  • PCIe up to Gen5.0
  • Ethernet 10G, 25G, 50G, 100G
  • JESD204B/C, D-compatible
  • SATA up to rev 3.0
  • RapidIO up to rev 4.0
  • Infiniband up to FDR
  • Programmable RX linear equalizer
  • Digital high speed PLL
  • Pattern Generator for diagnostics
  • Concurrent Eye Monitor for equalization and channel analysis
  • Far End and Near End Loopbacks
  • Analog testbus

Benefits

  • Drop-in (equal foot print and bump map) replaceable version for LR/MP (Long-Reach/Multi-Protocol) with up to 36dB channel insertion available as well

Applications

  • High-Speed I/O Interfaces: PCIe, RapidIO, SATA, others
  • Networking equipment and interfaces: for Ethernet standards, Infiniband, others
  • High-speed data-converters: DAC, ADC, etc.
  • Interfacing electronic equipment using high-speed optical interfaces
  • Serializer based proprietary protocols on board or back-plane level and with cabled connections
  • Low-latency Die-to-Die interconnects based on lean and cache-coherent protocols: CHI, AXI, AXI-lite, etc.

What’s Included?

  • Front- and backend integration views
  • LIB, LEF, CDL netlist, GDSII layout
  • Fast Verilog simulation models
    • Functional abstract, functional
    • RNM (real number model) (optional)
  • IBIS/AMI models
  • Sample testbench
  • Die-to-Die/CHI Controller RTL (optional)
  • Documentation
    • User Manual, Integration & DfT Guide
    • Control and Status Registers Manual
    • IPXACT memory map
    • Electrical characteristics, Silicon Report

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 12nm LP —

Specifications

Identity

Part Number
GF12-VSRPHY32G
Vendor
Extoll GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Extoll GmbH
HQ: Germany
Contact Extoll GmbH

Learn more about Multi-Protocol PHY IP core

How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity

Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is 32G Multi Rate Very Short Reach SerDes PHY - GlobalFoundries 12LP and 12LPP?

32G Multi Rate Very Short Reach SerDes PHY - GlobalFoundries 12LP and 12LPP is a Multi-Protocol PHY IP core from Extoll GmbH listed on Semi IP Hub. It is listed with support for globalfoundries.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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