How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
T2M GmbH
Category:
DDR
eDisplay Port v1.4 Rx PHY IP in 40LL, Silicon Proven in SMIC 40LL
The eDisplay Port v1.4 Rx PHY IP Core caters to chips requiring high-bandwidth communication with minimal power consumption.
Overview
The eDisplay Port v1.4 Rx PHY IP Core caters to chips requiring high-bandwidth communication with minimal power consumption. It serves as a multi-gigabit receiver macro compliant with eDP standards. This adaptable and dependable solution enables data reception speeds reaching 5.4Gbps, optimizing both power usage and die size. It boasts simplicity in production and integration into Video Interface systems. The AUX channel supports a bit rate close to 1Mbps, functioning as a half-duplex, bidirectional channel composed of a single differential pair. Each macro includes an AUX channel with one PLL and bias gen unit, along with multiple receiver channels. Essential functions of the receiver encompass a dedicated equalizer, clock and data recovery (CDR), S2P, and self-test features, with the ability to disable individual channels as needed.
Key features
- Low power operation: 22mW/lane @ typical
- Support data rate: 0.6Gbps~5.4Gbps
- Utilize 10bit parallel interface for per lane
- Independent power down control for each lane
- Implemented CTLE to compensate channel loss
- Integrated on-die termination resistors
- Tolerance maximum SSC ±15000ppm@30KHz
- AC coupling
- Support 4X, 8X, 16X channel configuration
- One independent PLL is shared in every macro
- Support PRBS loopback in every channel
- AUX channel included
- Support BGA, QFN/QFP package
- Metal option: 1P8M-7lc-1TMc-ALPA1
- Silicon Proven in SMIC 40LL
Block Diagram
eDisplay Port v1.4 Rx PHY IP in 40LL block diagram
What’s Included?
- Application Note / User Manual
- Behaviour model, and protected RTL codes
- Protected Post layout netlist and Standard
- Delay Format (SDF)
- Frame view (LEF)
- Metal GDS (GDSII)
- Test patterns and Test Documentation
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| SMIC | 40nm | LL | In Production |
Specifications
Identity
Part Number
eDisplay Port v1.4 Rx PHY IP in 40LL
Vendor
T2M GmbH
Type
Silicon IP
Controller / PHY
Controller + PHY
,
PHY
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Germany
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Frequently asked questions about DDR Interface IP
What is eDisplay Port v1.4 Rx PHY IP in 40LL, Silicon Proven in SMIC 40LL?
eDisplay Port v1.4 Rx PHY IP in 40LL, Silicon Proven in SMIC 40LL is a DDR IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for smic In Production.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.