Fully-integrated 4X PLL clock generator
IP
- Clock Generator
- now
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Fully-integrated 4X PLL clock generator
IP
Licensable baseband controller core + Licensable upper and lower protocol stacks
IP
Direct memory access controller with AHB interface
Direct memory access controller with AHB interface.
Scan Ring Linker enables multiple 1149.1 scan rings
Scan Ring Linker enables multiple 1149.1 scan rings
Embedded Configuration and Test Processor
Embedded Configuration and Test Processor
Fast Access Controller – a plug-and-play IP solution for fast embedded Flash Programming and Memory Testing
AMBA AHB to PCI Host Bridge
AMBA AHB Bus to SDRAM Controller
AMBA AHB Bus to SDRAM Controller
AMBA AHB Bus Master
AMBA AHB Bus Slave
PCI-to-PCI Bridge
PCI-ISA Bridge
UART
CompactFlash/PCMCIA Host Controller
CompactFlash/PCMCIA Host Controller
Pipeline SDRAM Controller
Clean-room clone of Z180 TM CPU
Clean-room clone of Z180 TM CPU
PCI Bus Arbiter
64-bit PCI Host Bridge
64-bit PCI Bus Target
64-bit PCI Bus Master/Target