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Intellitech® Corporation, the technology leader in solutions for IEEE 1149.1-2013 Silicon Instrument development, has announced it has been granted US patent 9,152,749 entitled "Management system, method and apparatus for licensed delivery and accounting of electronic circuits".
Intellitech® Corporation, the industry leader in solutions for IEEE 1149.1-2013 Silicon Instrument™ development, has announced interoperability between its NEBULA silicon debugger, iJTAGServer and Cadence® Incisive® Enterprise Simulator.
Intellitech has announced interoperability between its NEBULA silicon debugger, the Intellitech iJTAGServer bridge, and the Synopsys VCS® functional verification environment.
Intellitech announced today the availability of ISIS™, a simulation interface, which links Intellitech's on-chip debugger, NEBULA™, with the Mentor Graphics Questa® verification platform. IEEE 1149.1-2013 is the extensively revised version of the JTAG standard released by the IEEE in June of 2013 that adds hierarchical structural description languages for internal JTAG access and a hierarchical Procedure Definition Language (PDL).
Intellitech Corporation announced today that the proposed IEEE 1149.1-2012 JTAG standard has reached consensus with an eighty-five percent approval in a recent IEEE ballot. The standard incorporates industry best practices for enabling IC test re-use from silicon to systems.
Intellitech announced today a free version of its NEBULA software to enable FPGA and SoC designers to develop and validate JTAG/IJTAG based infrastructure IP. The software is targeted for designers who want to validate internal JTAG accessible IP blocks and instruments using the PDL language of upcoming 1149.1-2011 and future IEEE P1687.