Vendor: Eureka Technology, Inc. Category: PCI

PCI-ISA Bridge

PCI-ISA Bridge

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Key features

  • Compliant with PCI bus specification 2.1 and 2.2.
  • Convert PCI transaction to ISA bus transaction.
  • Function as PCI target on PCI bus.
  • Function as ISA master on ISA bus.
  • Map PCI address space to ISA address space through Base Address Register.
  • Supports 16-bit and 8-bit data transfer, memory and IO transfers on ISA bus.
  • ISA bus operates on one-fourth the frequency of the PCI clock.
  • Performs multiple ISA operations to transfer each 32-bit PCI word.
  • Write buffer to speed up PCI-to-ISA write transfer.
  • Support ISA devices with different speed by using NOWS# and CHRDY signals.
  • Parity generation and parity error detection on PCI bus.
  • Includes all PCI specific configuration registers.
  • Fully synchronous design, no gated clock or transparent latch. All flip-flops are rising edge trigger.

Block Diagram

EC150 block diagram

Specifications

Identity

Part Number
EC150
Vendor
Eureka Technology, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Eureka Technology, Inc.

Learn more about PCI IP core

PCI Express 3.0 needs reliable timing design

PCI Express (PCIe) is an important standard for chip-to-chip communications and serves as a standard for connecting motherboards to peripheral cards. It can be challenging, however, to implement the reference clock so that it meets the various requirements of the PCIe standard.

Frequently asked questions about PCI IP cores

What is PCI-ISA Bridge?

PCI-ISA Bridge is a PCI IP core from Eureka Technology, Inc. listed on Semi IP Hub.

How should engineers evaluate this PCI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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