How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Eureka Technology, Inc.
Category:
DDR
Pipeline SDRAM Controller
Pipeline SDRAM Controller
Key features
- Designed with synthesizable HDL for ASIC and PLD synthesis.
- Supports both discrete SDRAM chips and PC100/133 SDRAM DIMM.
- Supports register mode and non-register mode SDRAM DIMM.
- Supports industrial standard SDRAM from 64Mbit to 512Mbit device sizes.
- Page hit detection to support multiple column accesses within the same row.
- Pipeline access allows continuous data bursting.
- Programmable memory size: 4, 8, 16 and 32 bits per SDRAM.
- Programmable word size:16, 32 and 64 bits.
- Supports all burst lengths: 1, 2, 4, 8 and full page.
- Zero wait state burst data transfer.
- Programmable SDRAM access timing parameters.
- Supports multiple external SDRAM banks.
- Automatic refresh generation with programmable refresh intervals.
- Programmable memory configuration registers.
- Differentiating Features
- Power saving mode.
- ECC or parity support.
Block Diagram
EP525 block diagram
Specifications
Identity
Part Number
EP525
Vendor
Eureka Technology, Inc.
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about DDR Interface IP
What is Pipeline SDRAM Controller?
Pipeline SDRAM Controller is a DDR IP core from Eureka Technology, Inc. listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.