Vendor: Intellitech Corp. Category: Test / Debug

Scan Ring Linker enables multiple 1149.1 scan rings

Scan Ring Linker enables multiple 1149.1 scan rings

Key features

  • High-Speed 1149.1 routing
    • Better signal integrity for TCK/TMS signals
    • SRL provides superior distribution of TCK, TMS and TRST signals permitting high-speed test operation greater than 40Mbs/sec. PCB engineering is also reduced as SRL eliminates complex test signal routing.
  • Reduces part costs
    • SRL can be deployed as a single IC on a PCB to reduce the need for buffers and logic level translators. SRL permits devices in secondary scan chains to have their IO pins configured at different voltage levels. A single SRL device controls each scan chain regardless of their voltage.
  • Flexible implementation
    • SRL simplifies design with plug-and-play IP that is easily embedded into a CPLD, FPGA or ASIC.
  • High fault coverage on difficult to test signals
    • SRL enables high fault coverage with pin level diagnostics for 1149.1 test signals -- TCK, TMS, TDI, TDO. Each TCK, TMS, TDI and TDO pin has a boundary-scan cell that can be used to test for shorts and stuck-at faults.

Specifications

Identity

Part Number
SRL (TM)
Vendor
Intellitech Corp.
Type
Silicon IP

Files

Product Sheet Download

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Provider

Learn more about Test / Debug IP core

Intellitech Granted US Patent for Pay-per-Instance IP core Licensing

Intellitech® Corporation, the technology leader in solutions for IEEE 1149.1-2013 Silicon Instrument development, has announced it has been granted US patent 9,152,749 entitled "Management system, method and apparatus for licensed delivery and accounting of electronic circuits".

New Software for Mentor Graphics Questa Platform Enables Early Verification of IEEE 1149.1-2013 Compliant IP and On-Chip Instruments

Intellitech announced today the availability of ISIS™, a simulation interface, which links Intellitech's on-chip debugger, NEBULA™, with the Mentor Graphics Questa® verification platform. IEEE 1149.1-2013 is the extensively revised version of the JTAG standard released by the IEEE in June of 2013 that adds hierarchical structural description languages for internal JTAG access and a hierarchical Procedure Definition Language (PDL).

Frequently asked questions about SerDes Test / Debug IP cores

What is Scan Ring Linker enables multiple 1149.1 scan rings?

Scan Ring Linker enables multiple 1149.1 scan rings is a Test / Debug IP core from Intellitech Corp. listed on Semi IP Hub.

How should engineers evaluate this Test / Debug?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Test / Debug IP.

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