Vendor: Eureka Technology, Inc. Category: PCI

64-bit PCI Bus Target

64-bit PCI Bus Target

Key features

  • Fully supports PCI specification 2.1 and 2.2 protocol.
  • Supports both 64-bit and 32-bit bus systems.
  • Supports dual address cycle (DAC) 64-bit addressing.
  • Designed for ASIC and PLD implementations.
  • Fully static design with edge triggered flip-flops.
  • Combined bus master and target functions.
  • Efficient back-end interface for different types of bus slave and master devices.
  • Zero wait state burst data transfer.
  • Automatic transfer restart on target retry and disconnect.
  • High speed bus request and arbitration.
  • Parity generation and parity error detection.
  • Includes all PCI specific configuration registers.
  • Optimized for devices with slow output enable control.
  • Differentiating Features
    • Multiple base address registers.
    • Address and data multiplexing.
    • Dual address cycle
    • Asynchronous clock domain.
    • Direct FIFO interface.
    • Variable burst length.
    • Target burst, target retry, disconnect and abort.

Block Diagram

Specifications

Identity

Part Number
EC140
Vendor
Eureka Technology, Inc.
Type
Silicon IP

Files

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Provider

Learn more about PCI IP core

PCI Express 3.0 needs reliable timing design

PCI Express (PCIe) is an important standard for chip-to-chip communications and serves as a standard for connecting motherboards to peripheral cards. It can be challenging, however, to implement the reference clock so that it meets the various requirements of the PCIe standard.

Frequently asked questions about PCI IP cores

What is 64-bit PCI Bus Target?

64-bit PCI Bus Target is a PCI IP core from Eureka Technology, Inc. listed on Semi IP Hub.

How should engineers evaluate this PCI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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