How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Eureka Technology, Inc.
Category:
DDR
AMBA AHB Bus to SDRAM Controller
AMBA AHB Bus to SDRAM Controller
Key features
- SDRAM controller interfaces directly with AHB Bus and user interface.
- Dual write buffer for simultaneous write posting and SDRAM access.
- Dedicated read buffer with data width matching.
- Early burst termination and CPU master busy on the AHB bus are supported.
- Supports AHB bus data width of 8, 16 and 32 bits.
- Zero wait state burst data transfer on both AHB interface and SDRAM.
- Supports industrial standard SDRAM from 64Mbit to 256Mbit device sizes.
- Pipeline access allows continuous data transfer without wasted cycle.
- Fast page access on row address matching.
- Independent row address matching for each of the 4 SDRAM banks.
- Programmable SDRAM access timing parameters.
- Automatic refresh generation with programmable refresh intervals.
- Optimized for ASIC and FPGA implementations.
- Differentiating Features
- Multi port input.
- Mobile DDR.
- Multiple clock domain for user ports.
- Multiple SoC and FPGA standard bus interface support (e.g. AHB-Lite, Avalon, PowerPc, Wishbone, SH4).
- Different data with matching.
Block Diagram
EP504 block diagram
Specifications
Identity
Part Number
EP504
Vendor
Eureka Technology, Inc.
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about DDR Interface IP
What is AMBA AHB Bus to SDRAM Controller?
AMBA AHB Bus to SDRAM Controller is a DDR IP core from Eureka Technology, Inc. listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.