GPU IP Listing

The UALink IP solution, consisting of UALink Controller, PHY, and verification IP, is designed to meet the performance requiremen…

• UALink

The Synopsys Foundation IP optimized for the TSMC’s 22nm Ultra Low Leakage (ULL) process provides designers an extensive offering…

• TSMC
• 22nm
• ULL
• Available on request

Built on our latest Xtensa NX architecture and offers up to 2.18TOPS of performance The Cadence® Tensilica® Vision Q7 DSP deliver…

• DSP Core
• Available on request

The DisplayPort Forward Error Correction (FEC) Transmitter IP core implements Reed-Solomon FEC and symbol interleaving as specifi…

• Channel Coding
• VESA DisplayPort 1.4

The HDMI Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol mapping/interleaving as specif…

• HDMI

Automotive applications are uniquely demanding for any AI acceleration solution.

• NPU

AMBA® ACE and CHI coherent interconnect technologies enable an entirely new class of high-performance datacenter applications in …

• Verification IP

Flow's Parallel Processing Unit solves one of computing's most fundamental dilemmas - parallel processing.

• Vector Processor

Industry's first FPGA-based hardened CXL IP solution for Type 1, 2, and 3 devices.

• CXL

PCIe Gen 6 Phy

• Multi-Protocol PHY

PCIe Gen 4 Verification IP ensures efficient, high-speed signaling, protocol conformance, error handling, and system interoperabi…

• Verification IP
• PCIe 4.0

The GDDR5 Memory Controller Verification IP (VIP) is a robust solution designed to verify the compliance and performance of GDDR5…

• Controller

Secure RoT with Post-Quantum Cryptography Datacenter-class SoCs such as CPUs, GPUs, DPUs, and NVMe controllers require a trusted …

• Root Of Trust

The GDDR7 controller IP core is designed for use in applications requiring high memory throughput including artificial intelligen…

• Controller

The DisplayPort Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol interleaving as specifi…

• Channel Coding
• VESA DisplayPort 1.4

The MIPS I8500™ Multi-Processing System (MPS) builds on a long history of high performance multi-threaded and multiprocessor IP p…

• DMA

The SEERIS Graphics Engine is a building block concept combining a collection of 2D graphics processing units with focus on blit …

• Display Controller
• Silicon Proven
• Available

The SEERIS Graphics Engine is a building block concept combining a collection of 2D graphics processing units with focus on blit …

• Vision Subsystem
• Silicon Proven
• Available
• All common input capture fo…

The SEERIS Graphics Engine is a building block concept combining a collection of 2D graphics processing units with focus on blit …

• GPU
• Silicon Proven
• Available

Industry- Performance and Efficiency for Inference at the Edge Based on a new, class- architecture, the Arm ML processor’s optimi…

• Edge AI Accelerator