Automotive applications are uniquely demanding for any AI acceleration solution. The combination of very high TOPS performance requirements coupled with very long lifespans of the product and the need to conform to evolving safety standards presents the automotive component supplier with a sticky dilemma: How to attain very high efficiency and performance density per watt combined with flexibility to run as-yet-undiscovered new AI/ML models all while navigating the years-long automotive grade product development and safety certification challenges? Data-center grade GPUs provide the desired flexibility but burn far too much power. Traditional NPU accelerators for SoCs yield the necessary energy efficiency but are inflexible – often not able to run new models that appear 12 months after selection let alone 12 years after the SoC tapeout.
The Chimera GPNPU processors deliver the SDV vision. Chimera processors blend the power efficiency of an accelerator with the full 100% programmability of a processor in automotive grade solutions that scale up to 864 TOPs. Whatever new form of AI networks are invented over the next decade, today's Chimera GPNPUs will run those networks with high performance.
Designed for functional safety
With financial backing from a leading Tier 1 automotive component supplier, Quadric’s processors and software toolchain are designed with automotive use cases as a prime focus. The Safety Enhanced (SE) versions of the Chimera QC series GPNPUs and the multicore Chimera QC-Multi series feature hardware mechanisms for soft error resiliency, watchdog timer support and redundant lockstep system design. Backed by comprehensive safety documentation and a safety manual, Quadric works with licensees to custom craft the appropriate safety analysis documentation for each specific automotive safety use case.
In-Cabin MONITORING
Single-core Chimera SE edition GPNPUs scale up to 108 TOPS to power camera-based solutions for driver monitoring, gesture control, or cabin occupant safety monitoring. With proven inference modalities spanning gaze detection, pose detection, gesture recognition and object detection and classification any functionality you can imagine can be implemented running on a Chimera GPNPU processor.
Radar, LIDAR and Camera Processing – DSP Plus AI
Distributed sensor architectures that process radar, lidar or camera inputs at the sensor source need to combine traditional DSP signal processing with AI / machine learning inference algorithms. Quadric Chimera GPNPUs uniquely allow the mixing and matching of both traditional C++ signal processing code plus graph-based networks on one single processing engine. This combination of coding styles on one processor pipeline guarantees flexible future-proofing for all possible algorithmic changes your product might need to support over the entire product life cycle.
High-Performance ADAS Compute
Multicore Chimera QC-Multi Series GPNPUs scale up to 864 TOPS. The industry-leading Chimera Graph Compiler splits workloads to compile large input image networks and automatically tiles the image over multiple cores to scale up performance for image sizes up to 4K resolution. And multicore Chimera clusters can also run different workloads on different sub-cores simultaneously for large scale accelerated compute of disparate workloads.
