SDI Verification IP implements the digital transmision systems as specified in Serial-Digital Interface standard for microprocess…
- Verification IP
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
SDI Verification IP implements the digital transmision systems as specified in Serial-Digital Interface standard for microprocess…
SD Express Verification IP is an solution in the market for the verification of SD Express implementations.
Safe-By-Wire Plus Verification IP
Safe-By-Wire Plus (SBWP) Verification IP is an solution in the market for the verification of Safe-By-Wire Plus (SBWP) two-wire s…
SATA Verification IP provides an smart way to verify the SATA bi-directional bus.
SAS Verification IP provides an smart way to verify the SAS bi-directional bus.
SafeSPI is the serial synchronous communication protocol based Flash VIP, supporting all major SafeSPI vendors.
SENT (SAE J2716) Verification IP
Single Edge Nibble Transmission (SENT) is a single-wire, serial unidirectional communication protocol.
SAE_J1850 Verification IP provides an smart way to verify the SAE_J1850 component of a SOC or a ASIC.The SmartDV's SAE_J1850 Veri…
RoE Verification IP is compliant with IEEE 1914.3-2018 for Radio over Ethernet Encapsulations and Mappings and IEEE 802.3 Specifi…
RoCE Verification IP is compliant with InfiniBandTM Architecture Specification Volume 1 Release 1.2.1 for RDMA Over Converged Eth…
RapidIO Verification IP provides an smart way to verify the RapidIO bi-directional two-wire bus.
QSPI (Quad Serial Peripheral Interface) Verification IP
QSPI (Quad Serial Peripheral Interface) VIP can be used to verify Master or Slave device following the QSPI basic protocol.It can…
QI Verification IP provides a smart way to verify the Qi component of a SOC or a ASIC.
PVCI (Peripheral VCI) Verification IP
PVCI (Peripheral VCI) Verification IP provides an smart way to verify the PVCI (Peripheral VCI) component of a SOC or a ASIC.
PMBus Verification IP provides an smart way to verify the PMBus component of a SOC or a ASIC.
PDM can digitally represents high quality audio, and is inexpensive and easy to implement.
PCIe Verification IP provides an smart way to verify the PCIe bi-directional bus.
PCI Verification IP provides an smart way to verify the PCI bi-directional bus.
The SmartDV's ORAN Verification IP is fully compliant with ORAN Specification V6.0 and IEEE 802.3 specifications.
Open LVDS Display Interface (OpenLDI) Verification IP
Open LVDS Display Interface(OpenLDI) specification was developed through the cooperation of companies in the semiconductor, displ…