Vendor: Thesys-Intechna Category: Analog Front End

SPDT Analog Switch

The TI-RF-Switch is a broad-band dual SPDT analog switch containing two single-pole double-throw switches.

Overview

The TI-RF-Switch is a broad-band dual SPDT analog switch containing two single-pole double-throw switches. Used CMOS XH035 technology provides high isolation and low insertion loss at frequencies up to 1 GHz. The analog switch includes an integrated control logic scheme, which eliminates the necessity of applying of external control circuitry. Logic control inputs of the device are compatible with CMOS and LVTTL logic levels.

Key features

  • Voltage transmission coefficient: 0.95/0.94/0.93 at 0.1/0.5/1 GHz input
  • Switching time: 9 ns
  • Isolation: 64/47/41 dB at 0.1/0.5/1 GHz input
  • Video feedthrough: 5.5 mV
  • Operating temperature range: -60 °C to +125 °C
  • Supply voltage: 2.3 V to 3.5 V

Block Diagram

Benefits

  • Two totally independent SPDT switches in a chip
  • Inputs and outputs isolated by metallization layers
  • High frequency signal inputs separated by ground supplies up to the chip level
  • 50 ? terminated shunt legs
  • Good VSWR in each output regardless of the switch mode

Applications

  • Wireless communications
  • Radio frequency signals switching

What’s Included?

  • Datasheet
  • GDSII database
  • Customer support

Specifications

Identity

Part Number
TI-RF-Switch
Vendor
Thesys-Intechna
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Russia

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Frequently asked questions about Analog Front End IP cores

What is SPDT Analog Switch?

SPDT Analog Switch is a Analog Front End IP core from Thesys-Intechna listed on Semi IP Hub.

How should engineers evaluate this Analog Front End?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Analog Front End IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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