Vendor: Enclustra GmbH Category: Display Controller

Display Controller

The Display Controller IP Core enables the easy addition of a display to existing or future FPGA designs, allowing the system des…

Overview

The Display Controller IP Core enables the easy addition of a display to existing or future FPGA designs, allowing the system designer to focus on the main application instead of dealing with display control issues. In addition, there is no need for an external display controller device that would consume precious PCB space and unnecessarily extend the project’s BOM.

With its modular design and strong scalability, the Display Controller IP Core perfectly fits the system requirements without wasting any FPGA resources. These unique features will also simplify the reuse of the Display Controller IP Core in future projects. Selecting our Display Controller IP Core for the display control needs of present or future projects will significantly reduce time to market as well as the overall system cost.

Key features

  • Support for parallel, LVDS, HDMI/DVI and CameraLink displays without external display controller device
  • Support for unlimited video pages
  • Built-in PWM generator for display brightness control
  • Optional 2D accelerator unit (draw/copy rectangles, supports transparent color)
  • AXI/Avalon bus interface for both register bank and frame buffer memory access
  • Supported color modes:
    • 16-bit true color (5/6/5)
    • 24-bit true color
  • Supported display resolutions:
    • Up to 1280 × 1024 on low-cost FPGAs*
    • Up to 1920 × 1080 on high-performance FPGAs1
    • 1 Note that these resolutions are for reference only and thus not guaranteed; the maxium achievable resolution is dependent on system design factors like memory bandwidth, clock frequency, etc.

Block Diagram

Benefits

  • No need for an external display controller device which results in a smaller PCB and a reduced BOM
  • Low resource usage and good scaling due to modular design
  • Easy integration thanks to the unified bus interface and the clearly laid out register bank

Applications

  • Test and measurement
  • Communication
  • Automation
  • Embedded processing
  • Medical diagnostics

What’s Included?

  • Display Controller IP Core
    • VHDL source files (plain or encrypted, depending on product options)
    • Precompiled ModelSim® simulation libraries (planned)
    • User manual (PDF download)
  • Display Controller IP Core reference design
    • Reference design top-level VHDL file (plain VHDL)
    • UCF / XDC / SDC constraint files (depending on product options)
    • Xilinx® ISE / Xilinx Vivado™ / Altera® Quartus® II project files (depending on product options)
    • Top-level simulation test bench file (plain VHDL) (planned)
    • Top-level simulation ModelSim project file (planned)
    • Documentation (integrated in user manual)

Specifications

Identity

Part Number
Display Controller
Vendor
Enclustra GmbH
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Switzerland

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Frequently asked questions about Display Controller IP

What is Display Controller?

Display Controller is a Display Controller IP core from Enclustra GmbH listed on Semi IP Hub.

How should engineers evaluate this Display Controller?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Display Controller IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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