MPEG-1/2 - Layer I/II Audio Encoder
The MPEG-1/2 – Layer I/II Audio Encoder (CWda74) is an audio IP core for encoding one audio stream in real-time(1).
- Audio Analog
- Silicon and FPGA proven
- Now
- ISO/IEC 11172-3 and 13818-3
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
MPEG-1/2 - Layer I/II Audio Encoder
The MPEG-1/2 – Layer I/II Audio Encoder (CWda74) is an audio IP core for encoding one audio stream in real-time(1).
SATA 3 Host Controller on ARRIA V FPGA
The LDS SATA 3 HOST AR5GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA …
HDLC & SDLC Protocol Controller
The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC…
Foundry Sponsored - Single Port SRAM compiler - TSMC 130 nm BCD - Memory optimized for ultra high density and high speed - compil…
Foundry sponsored - Dual Port SRAM compiler - TSMC 90 nm LPeF - Memory otimized for high density and low power - compiler range u…
Foundry sponsored - Dual Port SRAM compiler - TSMC 90 nm LPeF - Memory optimized for high density and low power - compiler range …
MPEG-2 Transport Stream Encapsulation for SMPTE2022
The IPX-MPEG2-TS IP-cores are designed to be used with intoPIX video codecs.
VeriSilicon SMIC 0.25um High-Speed Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Corporatio…
Foundry sponsored - Single Port SRAM compiler - TSMC 90 nm uLL - Memory optimized for ultra low leakage - Dual Voltage - compiler…
IMG CXM GPU: Seamless visuals
Configurable CAN Bus Controller
The core is a standalone controller for the Controller Area Network (CAN), widely used in automotive and industrial applications.
SPI Master/Slave- Serial Peripheral Interface
The SPI core is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of a serial clock…
JPEG 2000 HD encoder board, is a PCI-Express acceleration board for performing JPEG 2000 compression.
JPEG 2000 HD decoder board, is a PCI-Express acceleration board for performing JPEG 2000 decompression.
The S8051XC3 IP core implements a high-performance, low-energy, 8-bit microcontroller that executes the MCS®51 instruction set an…
Implements MIL-STD-1553 serial data bus.
DO-254 Soft Error Mitigation Controller 1.01a
The Soft Error Mitigation (SEM) IP core performs SEU detection, correction, and classification.
SATA Device Controller on Kintex 7
The LDS SATA 3 DEVICE XK7 IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Kintex…
Multi-Video-Source Multiplexing Serial Video Transmitter for MIPI CSI2
The SVT-CS4AP2 supports MIPI CSI2 over MIPI D-PHY.
triple-speed (10Mbps/100Mbps/1Gbps) Ethernet controller
The Flexibilis Ethernet Controller (AFEC) is a triple-speed (10Mbps/100Mbps/1Gbps) Ethernet controller IP block that can be emplo…