Overview
JPEG 2000 HD decoder board, is a PCI-Express acceleration board for performing JPEG 2000 decompression. It is compatible with the JPEG 2000 HD encoder board and can process 90 frames per second in 1080p (1920x1080) resolution. The
decoder board combines performance, robustness and high quality to provide a solution for decoding high-definition content.
Its compactness makes the decoder board an excellent alternative to PC clusters, offering real-time decoding capability in a PCIe form factor. Moreover it is built on FPGA technology, which offers the advantages of flexibility and upgradeability.
JPEG 2000 HD decoder board can be used for various broadcast or other applications, including monitoring, distribution, archiving, production, etc
Learn more about Video Processing IP core
This paper describes an FPGA-based high-definition video processing platform. The platform supports a wide range of applications including flat-panel TV, projection TV and video monitor.
Configurable Processors for Video Processing SOCs
Programmable FPGA devices are the perfect choice for interfacing with multiple high-resolution image sensors simultaneously...
A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing
Building a high-performance, quad-channel H.264 encoder using low-cost, low-power FPGA architecture.
Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.
