The HDMI 2.0 TX (Transmitter) is a multimedia interface designed to deliver high-definition video and audio from source devices t…
- Single-Protocol PHY
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The HDMI 2.0 TX (Transmitter) is a multimedia interface designed to deliver high-definition video and audio from source devices t…
The Embedded DisplayPort (eDP) 1.3 Transmitter PHY is a high-performance interface IP designed to enable the transmission of vide…
Our silicon proven Automotive IP Suite offers versatile and robust IP solutions for high-speed data communication in automotive a…
MIPI CD PHY Combo TX & RX + DSI & CSI Controller
Our MIPI CD-PHY Transmitter and receiver PHY with Display Serial Interface (DSI) and Camera Serial Interface (CSI) Controllers ar…
MIPI D-PHY TX & RX + DSI & CSI Controllers
Our MIPI D-PHY Transmitter and receiver PHY with Display Serial Interface (DSI) and Camera Serial Interface (CSI) Controllers are…
Our LPDDR5X PHY is a cutting-edge, high-performance physical layer interface PHY designed to meet the demanding requirements of m…
Our DDR and LPDDR Combo PHY is a versatile and high-performance solution designed to meet the memory interface needs of modern co…
4800 ONFI NV-DDR3 and NV-LPDDR4 with 4-tap DFE
Our 4800 ONFI PHY is a IP solution, including I/O, PMA, PCS and test engine with four-tap DFE.
3600 ONFI NV-DDR3 and NV-LPDDR4 with Optional DFE
Our 3600 ONFI PHY is a silicon proven IP solution, including I/O, PMA, PCS and test engine with optional one-tap DFE.
Our mass production-proven IPTD2D-A D2D Interconnect IP Solutions offer industry- power efficiency, performance, and low latency,…
The UCIe-S 64GT/s PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-high-speed interconnects betwee…
The UCIe-A 64GT/s PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-high-speed interconnects betwee…
Low Latency Ethernet 10G/25G MAC
The German Fraunhofer Heinrich-Hertz-Institute (HHI) partners with MLE to commmercialize and market HHI’s proven network technolo…
Fully synthesizable and configurable memory subsystem IP that enables significant improvement in power, performance and endurance…
, patented memory technology based on industry proven MRAM.
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of D…
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of D…
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of D…
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of D…
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of D…