Vendor: InPsy Category: LPDDR

DDR and LPDDR Combo PHY

Our DDR and LPDDR Combo PHY is a versatile and high-performance solution designed to meet the memory interface needs of modern co…

Controller + PHY + 1 View all specifications

Overview

Our DDR and LPDDR Combo PHY is a versatile and high-performance solution designed to meet the memory interface needs of modern computing systems. This multi-standard PHY supports different types of DDR and LPDDR, providing flexibility and future-proofing for various applications including high-performance computing, mobile devices, and data centers. It ensures robust performance with high data rates, low latency, and efficient power consumption.

Key features

  • Supports multiple combinations of DDR/LPDDR interfaces
    • DDR3, DDR3L, DDR4 and LPDDR4 combo PHY
    • LPDDR4X and LPDDR5 combo PHY
    • LPDDR5 and LPDDR5X combo PHY
    • DDR4, DDR5 and LPDDR4 combo PHY
    • DDR4, DDR5, LPDDR4, LPDDR4X combo PHY
    • Etc.
  • Compliant with JEDEC DDR and LPDDR standards
  • Supports all auto calibrations
    • Impedance calibration
    • Delay measurement for clock period
    • Write-leveling and gate training (per DRAM specification)
    • Read and Write data eye training
    • Per-bit, per-rank delay controllable (including CA/DQ/DQS)
    • Etc.
  • Industry leading area and power
  • Robust Signal Integrity: Advanced equalization and timing features to ensure reliable data transmission
  • Supports DDR/LPDDR I/O with power-down retention
  • Supports CA and DQ signal swap table for easy system integration
  • Supports LPDDR Dynamic Voltage and Frequency Scaling (DVFS)
  • Compliant with AMBA APB3.0 for register accessing

Specifications

Identity

Part Number
DDR and LPDDR Combo PHY
Vendor
InPsy
Type
Silicon IP
Controller / PHY
Controller + PHY , PHY

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Taiwan (R.O.C.)

Learn more about LPDDR IP core

InPsytech showcases 3nm UCIe 3.0 technology at OCP 2025, Accelerating Innovation in Chiplet Ecosystem

InPsytech has long focused on high-speed and low-power interface IP technologies. Its UCIe (Universal Chiplet Interconnect Express) portfolio supports advanced process nodes from 22nm down to 2nm, optimized for 3nm production. The IP achieves data transfer rates up to 64 GT/s, while supporting 2.5D and 3D packaging architectures to enable high-efficiency chip-to-chip interconnects and heterogeneous integration.

Frequently asked questions about LPDDR Interface IP

What is DDR and LPDDR Combo PHY?

DDR and LPDDR Combo PHY is a LPDDR IP core from InPsy listed on Semi IP Hub.

How should engineers evaluate this LPDDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LPDDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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