UCIe-S 64GT/s PHY IP

The UCIe-S 64GT/s PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-high-speed interconnects between dies in standard packaging environments. Leveraging the UCIe (Universal Chiplet Interconnect Express) 3.0 standard, this IP supports a blistering data rate of up to 64Gbps per lane, enabling next-generation AI, HPC, and data center SoC applications.

• Data Rate: Up to 64GT/s per lane
• Power Efficiency: 0.25 ~ 0.8 pJ/bit (process and operating speed dependent)
• Beachfront and Depth per x16 & x32 module
  • Bump Pitch: 130um
  • Beachfront Bandwidth: ~1,143um
  • x16 Depth: 1,239um
  • x32 Depth: 2,478um
• Supports Standard Packages
  • MCM package on substrate
  • Chiplet-to-Chiplet (C2C) with BGA package
• x16 or x32 Transmission and x16, x32 Receiving Lanes per module
• Supports @speed Manufacture Tests for both CP and FT with built-in programmable test patterns generator: PRBS7, PRBS23, or user-defined
• Supports broadcast register write to shorten programming time
• Per-bit real-time data eye monitor provides comprehensive insight into data transmission
• Firmware-based calibration and training allow fast product and system turnaround time Supports 3D package (UCIe v2.0)
• Low Latency: Sub-nanosecond latency for critical computing applications
• Robust Signal Integrity: Designed for high-performance computing environments with challenging noise and crosstalk conditions
• Beachfront Bandwidth per 1.0mm
  • 28 GB/s @4GT/s
  • 56 GB/s @8GT/s
  • 84 GB/s @12GT/s
  • 112 GB/s @16GT/s
  • 168 GB/s @24GT/s
  • 224 GB/s @32GT/s
  • 336 GB/s @48GT/s
  • 448 GB/s @64GT/s
  • Fully integrated solution with IPT UCIe Controller
• Supports IO bypass mode for easy system integration and user-defined applications