Vendor: InPsy Category: LPDDR

LPDDR5X PHY

Our LPDDR5X PHY is a cutting-edge, high-performance physical layer interface PHY designed to meet the demanding requirements of m…

Controller + PHY + 1 LPDDR5X View all specifications

Overview

Our LPDDR5X PHY is a cutting-edge, high-performance physical layer interface PHY designed to meet the demanding requirements of modern computing and mobile applications. This PHY supports the latest LPDDR5X standard, providing enhanced data rates, lower latency, and improved power efficiency. It is ideal for applications such as smartphones, tablets, laptops, and high-performance computing systems, where speed and energy efficiency are paramount.

Key features

  • Supports High Data Rate
    • 8,533 MT/s (5nm and 3nm)
    • 6,400 MT/s (16nm and 12nm)
  • Compliant with JEDEC LPDDR5X standards
  • Scalable Architecture: Supports multiple channels and ranks, offering flexibility for various memory configurations
  • Supports all auto calibrations
    • Impedance calibration
    • Delay measurement for clock period
    • Write-leveling and gate training (per DRAM specification)
    • Read and Write data eye training
    • Per-bit, per-rank delay controllable (including CA/DQ/DQS)
    • Etc.
  • Industry leading area and power
  • Robust Signal Integrity: Advanced equalization and timing features to ensure reliable data transmission
  • Supports I/O with power-down retention
  • Supports CA and DQ signal swap table for easy system integration
  • Supports Dynamic Voltage and Frequency Scaling (DVFS)
  • Compliant with AMBA APB3.0 for register accessing

Specifications

Identity

Part Number
LPDDR5X PHY
Vendor
InPsy
Type
Silicon IP
Controller / PHY
Controller + PHY , PHY

Standards & Interfaces

Memory
LPDDR5X

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

InPsy
HQ: Taiwan (R.O.C.)

Learn more about LPDDR IP core

InPsytech showcases 3nm UCIe 3.0 technology at OCP 2025, Accelerating Innovation in Chiplet Ecosystem

InPsytech has long focused on high-speed and low-power interface IP technologies. Its UCIe (Universal Chiplet Interconnect Express) portfolio supports advanced process nodes from 22nm down to 2nm, optimized for 3nm production. The IP achieves data transfer rates up to 64 GT/s, while supporting 2.5D and 3D packaging architectures to enable high-efficiency chip-to-chip interconnects and heterogeneous integration.

Frequently asked questions about LPDDR Interface IP

What is LPDDR5X PHY?

LPDDR5X PHY is a LPDDR IP core from InPsy listed on Semi IP Hub.

How should engineers evaluate this LPDDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LPDDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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