ONFI 5.2: What’s new in Open NAND Flash Interface's latest 5.2 standard
ONFI 5.2 is the latest generation of ONFI device standard, published in 2024. ONFI 5.2 devices have added several major features over previous generation ONFI standards.
Vendor:
InPsy
Category:
NAND Flash
4800 ONFI NV-DDR3 and NV-LPDDR4 with 4-tap DFE
Our 4800 ONFI PHY is a IP solution, including I/O, PMA, PCS and test engine with four-tap DFE.
Overview
Our 4800 ONFI PHY is a complete IP solution, including I/O, PMA, PCS and test engine with four-tap DFE. The IPT 4800 ONFI PHY facilitates high-speed data transfer between NAND flash memory and host controllers. This interface is crucial for enhancing the performance and reliability of storage solutions in various applications, from consumer electronics to industrial systems.
Key features
- Supports Both NV-DDR3 and NV-LPDDR4 with 4-tap DFEs
- NV-DDR3 up to 3,600 MT/s
- NV-LPDDR4 up to 4,800MT/s
- Support Decision Feedback Equalization (DFE): For extra high loading, DFE can reduce errors and improve data integrity
- Compliant with JEDEC 6.0 (TBD) and JESD 230G specifications
- Supports real-time PVT data-eye monitoring
- Supports all required trainings and calibrations
- Supports Power-Down Modes
- Active
- Low-power Run
- Sleep
- Low Power Sleep
- Standby
- Hibernate
- Compliant with AMBA APB3.0 for register accessing
Block Diagram
4800 ONFI NV-DDR3 and NV-LPDDR4 with 4-tap DFE block diagram
Specifications
Identity
Part Number
4800 ONFI NV-DDR3 and NV-LPDDR4 with 4-tap DFE
Vendor
InPsy
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Taiwan (R.O.C.)
Learn more about NAND Flash IP core
Concealable physical unclonable functions using vertical NAND flash memory
Here, the authors propose a concealable PUF using V-NAND flash memory by generating PUF data through weak Gate-Induced-Drain-Leakage (GIDL) erase. The differences in doping depth among V-NAND strings arising from the fabrication cause variations in GIDL erase performance. The resulting V-NAND PUF demonstrated ideal security characteristics while maintaining 100% accuracy under variations in read count and temperature.
NAND Flash Memory - Key Element For Your Multi-Die Systems Verification - Part 1
A Tour of the Basics of Embedded NAND Flash Options
Scaling NAND flash to 20-nm node and beyond
Intel-Micron have recently introduced a scalable planar NAND cell for the 20nm technology [1]. Replacement of conventional wrap floating gate (FG) NAND memory cell with a High-K/Metal gate planar cell that can scale to the 20nm node and beyond was a significant challenge and required comprehensive material and cell exploration and optimization. This paper discusses some of the fundamental cell design issues considered and addressed to arrive at this planar cell technology including the reasoning behind choosing the planar floating gate cell over the nano-crystal cell, and the nitride cell.
Cadence support for the Open NAND Flash Interface (ONFI) 3.0 controller and PHY IP solution + PCIe Controller IP opening the door for NVM Express support
Eric Esteve
Frequently asked questions about NAND Flash Interface IP
What is 4800 ONFI NV-DDR3 and NV-LPDDR4 with 4-tap DFE?
4800 ONFI NV-DDR3 and NV-LPDDR4 with 4-tap DFE is a NAND Flash IP core from InPsy listed on Semi IP Hub.
How should engineers evaluate this NAND Flash?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this NAND Flash IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.