MIPI I3C Master RISC-V based subsystem
RISC-V based MIPI I3C master interface has been developed to ease sensor system design architectures in mobile wireless products …
- RISC-V
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
MIPI I3C Master RISC-V based subsystem
RISC-V based MIPI I3C master interface has been developed to ease sensor system design architectures in mobile wireless products …
MIPI A-PHY v1.0 is a physical layer communication protocol designed for automotive applications, including driver assistance, aut…
The I3C interface for the communication of an Smart Secure Platform(SSP), as defined in ETSI using the Smart Secure Platform Comm…
The AXI MATRIX-IP component is a multi-layer interconnect implementation of the AXI protocol, which is designed for high-performa…
On-chip ESD/EOS/Latch up/EMC protection for high voltage and BCD processes
Design cost reduction Designing ESD protection can be very costly: frequently many test structures are required, analysis needs t…
Robust circuit and interface solutions
PhyStar® robust circuit and interface solutions, including custom digital I/O’s, circuits that handle transient disturbances (e.g.
Silvaco develops General Purpose I/O optimized for design flexibility, performance and ESD protection.
The PLUG module is a silicon-proven AXI-to-AXI bridge designed to provide data encryption and inline ECC for reliable and secure …
Standalone stateful hash-based signatures software library
The SHSlib is a standalone stateful hash-based signatures software library, which provides signature verification for stateful ha…
USB 3.2 - Validates high-speed USB designs for protocol compliance and performance
XtremeSilica’s USB 3.2 Verification IP offers a comprehensive solution for validating designs based on the USB 3.2 specification.
The NVMe Gen 5 Controller Verification IP ensures that storage systems operate efficiently at 32 GT/s data transfer rates.
H.265 - Efficient video compression for high-quality, low-bandwidth streaming
H.265 (HEVC) is a video compression standard that offers up to 50% better compression efficiency than H.264, reducing bandwidth u…
H.264 - Efficient video compression for high-quality streaming and playback
H.264 (also known as AVC) is a video compression standard that ensures high-quality video delivery with minimal bandwidth usage.
DDR5 Controller - Ensures high-speed, efficient operation and compatibility of memory controllers
DDR5 Verification IP supports data rates up to 8400 MT/s, ensuring high-performance memory controllers meet the latest standards …
UFS Controller - Verifies compliance and performance of UFS interfaces in SoCs
The UFS Controller Verification IP (VIP) ensures proper operation and compliance of UFS interfaces in SoC designs.
UCLe - Ensures reliable validation and efficient connectivity for chiplets
UCIe VIP is a solution for validating and ensuring compliance in multi-chip semiconductor systems.
UART - Ensures reliable serial communication and protocol compliance in SoCs
The UART Verification IP provides a comprehensive solution for validating UART communication interfaces in System-on-Chip (SoC) d…
TLS - Validates TLS protocols to ensure secure, encrypted data transmission
TLS Verification IP (VIP) ensures secure communication by validating TLS protocol implementations.
SPI - Verifies reliable data transfer and protocol compliance in SPI systems
SPI (Serial Peripheral Interface) is a high-speed, synchronous communication protocol that ensures reliable data transfer between…
SPI Flash Controller - Ensures reliable validation of SPI Flash memory controllers
The SPI Flash Controller Verification IP (VIP) is a tool for verifying and simulating SPI Flash memory controllers in SoCs.